Shan Kutagulla

I make new materials behave on real wafers, in real fabs.

Thin-film deposition and process integration, from every side of the industry.

Experience

PVD · ALD · CVD · CMP · integration
2026 – nowSan Jose, CA

Kepler Computing

Senior Process Scientist

Developing manufacturable ALD and PVD ferroelectric memory.

2025 – 2026Fremont, CA

Lam Research

Process Engineer

ALD and CVD process development for barrier films and metals. Received the Director's Spotlight Award and a breakout presentation at Lam's 2026 Engineering Technology Conference.

2023 – 2024Austin, TX

Intel

Technology Research Intern, CMP

Built the first machine-learning model of dielectric oxide CMP. Named Outstanding Intern in Technology Development.

2021Austin, TX

Samsung Austin Semiconductor

Process Integration Engineer, 14nm RF · Metal Ops intern in 2019

Process integration on a 14nm high-volume line, saving the fab $15M.

2023Austin, TX

Canon Nanotechnologies

Process R&D Applications Intern

Process R&D for nanoscale patterning.

2020, 2018Sunnyvale, CA

JSR Micro

R&D Engineering Intern, EUV Lithography Team

Materials R&D for lithography, including EUV.

2023 – 2024Austin, TX

BattGenie & New Dominion Enterprises

Technical Consultant

Technical consulting on battery testing.